DMAC简介

DMAC（AXI Direct Memory Access Controller）是一种高速、高吞吐量的通用 DMA 控制器，用于在系统内存和其他外设之间传输数据。
AXI 表示 Advanced eXtensible Interface，是一种高性能、低延迟的总线协议，用于连接不同的硬件模块，例如处理器、DMA 控制器、存储器、外设等
AXI DMAC 是一种特定于 AXI 总线的 DMA 控制器，支持高带宽、直接内存访问。它可以在内存和 AXI4-Stream 目标外设之间进行数据传输，例如高速转换器等。

AXI DMAC驱动

1.dmac设备树节点

先从设备树开始看吧，下面是一个dw dmac节点的一个示例，

        dmac: dma-controller@5700000 {
            compatible = "snps,axi-dma-1.01a";
            reg = <0x5700000 0x100000>;
            clocks = <&dmacoreclk>, <&dmacfgrclk>;
            clock-names = "core-clk", "cfgr-clk";
            interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

            dma-channels = <8>;
            snps,dma-masters = <2>;
            snps,data-width = <4>;
            snps,block-size = <512 512 512 512 512 512 512 512>;
            snps,priority = <0 1 2 3 4 5 6 7>;
            snps,axi-max-burst-len = <256>;
            status = "okay";
        };

根据dw文档，各个节点属性的含义如下，

Synopsys DesignWare AXI DMA Controller

Required properties:
- compatible: "snps,axi-dma-1.01a"
- reg: Address range of the DMAC registers. This should include
  all of the per-channel registers.
- interrupt: Should contain the DMAC interrupt number.
- dma-channels: Number of channels supported by hardware.
- snps,dma-masters: Number of AXI masters supported by the hardware.
- snps,data-width: Maximum AXI data width supported by hardware.
  (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
- snps,priority: Priority of channel. Array size is equal to the number of
  dma-channels. Priority value must be programmed within [0:dma-channels-1]
  range. (0 - minimum priority)
- snps,block-size: Maximum block size supported by the controller channel.
  Array size is equal to the number of dma-channels.

Optional properties:
- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
  in this property. If this property is missing the maximum AXI burst length
  supported by DMAC is used. [1:256]

Example:

dmac: dma-controller@80000 {
    compatible = "snps,axi-dma-1.01a";
    reg = <0x80000 0x400>;
    clocks = <&core_clk>, <&cfgr_clk>;
    clock-names = "core-clk", "cfgr-clk";
    interrupt-parent = <&intc>;
    interrupts = <27>;

    dma-channels = <4>;
    snps,dma-masters = <2>;
    snps,data-width = <3>;
    snps,block-size = <4096 4096 4096 4096>;
    snps,priority = <0 1 2 3>;
    snps,axi-max-burst-len = <16>;
};